Clock Concurrent Optimization

Ten years ago, the EDA industry faced a crippling divergence in timing between RTL synthesis and placement caused by rapidly rising wire capacitances relative to gate capacitances. Without some reasonable level of placement knowledge to give credible estimates of wire length, it was becoming impossible to measure design timing with any accuracy during RTL synthesis. At this time, placement tools were not directly aware of timing and focused instead on metrics indirectly related to timing, such as total wire length. As chip designs scaled to “deep sub-micron” geometries (180nm and 130nm), the change in timing around placement became so significant and unpredictable that even manual iterations between synthesis and placement no longer converged. The solution was to re-invent placement, making it both directly aware of timing and also weaving in many of the logic optimization techniques exploited during RTL synthesis (for example, gate sizing and net buffering). This process was not easy, and ultimately we saw a major turnover in the back-end design tool landscape as a new generation of “physical optimization” tools were developed, released, and proliferated throughout the chip design community.